In the context of IMEC vzw's research on Reconfigurable Hardware, a Coarse Grain Array needs to be implemented for the evaluation of DRESC, a compiler designed for ADRES, a family of Coarse Grain architectures.

The starting point was an existing Functional Unit described in VHDL. This was modified to optimally use the resources available in the Xilinx Virtex-II FPGA series. The optimized Functional Unit was extended with load/store instructions. A 4 by 4 array of these Functional Units was described. Around this array an additional reconfiguration interface was implemented for instruction input and data input and output.

The Coarse Grain Architecture was described in VHDL. The functionality of all components and the system was proven with simulations in ModelSim.

The system performance was verified for an image processing application. A basic convolution filter with a 3 by 3 coefficient matrix for 10 by 10 RGB images, was written, manually mapped and simulated. The mapped algorithm has an Instruction Level Parallelism of 7.125 and finishes in about 1000 clock cycles. Execution of this application on a TI-C62 DSP needed twice as much cycles as on the array, noting that neither mapping was optimal. The design was synthesized to two target technologies to obtain estimations on the resource consumption. Synthesis to a Virtex-II 6000 component with Synplify yielded a 25% usage of slices: 3300 flip-flops and 14600 LUTs with a maximum clock frequency of 40MHz. Synthesis to UMC 130nm Standard Cell Technology resulted in a 2.48mm² silicon area and 970mW power consumption at a clock frequency of 500MHz.